1. Field of the Invention
The present invention relates to a comparator system and a method for comparing an input signal with a reference voltage using the system. More specifically, the present invention relates to a comparator system and a method for comparing an input signal, such as a multiplex data signal for VPS (Video Program System) or PDC (Program Delivery Control), with a reference voltage, which can be preferably used for, for example, retrieving a data signal such as a VPS signal and a PDC signal from a multiplied broadcasting signal during the vertical blanking intervals.
2. Description of the Background
The following description sets forth the inventor's knowledge and should not be construed as an admission that the description constitutes prior art.
FIG. 7 shows a conventional comparator 101, and FIG. 8 is a timing chart showing the operation of the comparator shown in FIG. 7.
In FIG. 7, the reference numeral 101 denotes a comparator having a (+) input terminal (non-inverting input terminal) to which a vide signal S is applied, a (−) input terminal (inverting input terminal) to which a reference voltage Vref is applied, and an output terminal from which an output signal is outputted. The comparator 101 is used for comparing the video signal S applied to the (+) input terminal with the reference voltage Vref applied to the (−) input terminal.
Here, it is assumed that the video signal S shown in FIG. 8(A) is applied to the (+) input terminal of the comparator 101. In this case, for the time period during the level of the video signal S is lower than that of the reference voltage Vref, the output of the comparator 101 is a low logic level (hereinafter simply referred to as “L level”). As the time passes, the level of the video signal S rises and then reaches the same level as the reference voltage Vref at the time point of T1. After this time point of T1, the level of the video signal S becomes higher than that of the reference voltage Vref. At this moment, the output of the comparator 101 ideally changes from the L level to a high logic level (hereinafter simply referred to as “H level”). In the actual comparator 101, however, the timing of the level change of the output of the comparator 101 from the L level to the H level delays by the delay time TdLH. Accordingly, the actual level change of the output delays by the delay time TdLH from the time point of T1.
On the other hand, for the time period during the level of the video signal S is higher than that of the reference voltage Vref, the output of the comparator 101 keeps the H level. As the time passes, the level of the video signal S starts to fall and then reaches the same level as the reference voltage Vref at the time point of T2. After this time point of T2, the level of the video signal S becomes lower than that of the reference voltage Vref. At this time point of T2, the output of the comparator 101 ideally changes from the H level to the L level. In the actual comparator 101, however, the timing of the level change of the output of the comparator 101 from the H level to the L level delays by the delay time TdHL. Accordingly, the actual level change of the output delays by the delay time TdHL from the time point of T2.
By repeating the aforementioned operations, the level comparison between the video signal S and the reference voltage Vref will be performed, and outputs can be obtained from the comparator 101.
As mentioned above, in the actual comparator 101, at the time of changing the output level from the L level to the H level and from the H level to the L level, a delay time TdLH and TdHL occurs inevitably. Furthermore, the length of the delay time TdHL and TdLH varies depending on the operating environments such as the amplitude of the input signal wave and/or the input voltage of the comparator, or the difference in circuit structure of the comparator. Accordingly, the length of the delay time TdHL and TdHL cannot be anticipated in advance, and the sensitivity of the comparator 101 will be affected by the length of the delay time TdLH and TdHL of the output. Thus, there is a drawback that the long and uncertain delay time causes a deterioration of the accuracy of the output data and the reliability of the comparator 101.
The description herein of advantages and disadvantages of various features, embodiments, methods, and apparatus disclosed in other publications is in no way intended to limit the present invention. Indeed, certain features of the invention may be capable of overcoming certain disadvantages, while still retaining some or all of the features, embodiments, methods, and apparatus disclosed therein.